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Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

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Abstract

A new technique for improving the performance of low-voltage folding ADC’s by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input–output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power dissipation of only 30 mW.

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Authors and Affiliations

  1. Electronics Research Center, Sharif University of Technology, P.O. Box 11365-8639, Azadi Ave, Tehran, Iran

    Hamid Movahedian Attar

  2. Electrical Engineering Department, Sharif University of Technology, P.O. Box 11365-8639, Azadi Ave, Tehran, Iran

    Mehrdad Sharif Bakhtiar

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  1. Hamid Movahedian Attar
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  2. Mehrdad Sharif Bakhtiar
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Correspondence to Hamid Movahedian Attar.

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Movahedian Attar, H., Bakhtiar, M.S. Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range. Analog Integr Circ Sig Process 61, 181–189 (2009). https://doi.org/10.1007/s10470-009-9282-1

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  • DOI: https://doi.org/10.1007/s10470-009-9282-1

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